SN54HC112, SN74HC112 Datasheet by Texas Instruments

U Ordering 2; Technical Design a 3 Support 5 o . quahly documentation development naming ' TEXAS INSTRUMENTS l} "3 TG ol nl cLK TG 7 TG ;(
SNx4HC112 Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset
1 Features
• Wide operating voltage range of 2 V to 6 V
• Outputs can drive up to 10 LSTTL loads
• Low power consumption, 40-μA max ICC
• Typical tpd = 13 ns
• ±4-mA output drive at 5 V
• Low input current of 1 μA max
2 Description
The ’HC112 devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at the
preset (PRE) or clear (CLR) inputs sets or resets the
outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J
and K inputs meeting the setup time requirements are
transferred to the outputs on the negative-going edge
of the clock (CLK) pulse. Clock triggering occurs at a
voltage level and is not directly related to the fall time
of the CLK pulse. Following the hold-time interval,
data at the J and K inputs may be changed without
affecting the levels at the outputs. These versatile flip-
flops perform as toggle flip-flops by tying J and K high.
Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
SN54HC112J CDIP (16) 24.38 mm × 6.92 mm
SN74HC112D SOIC (16) 9.90 mm × 3.90 mm
SN74HC112N PDIP (16) 19.31 mm × 6.35 mm
SN54HC112FK LCCC (20) 8.89 mm × 8.45 mm
SN54HC112W CFP (16) 10.16 mm × 6.73 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Functional Block Diagram
SN54HC112, SN74HC112
SCLS099H – DECEMBER 1982 – REVISED JUNE 2022
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Description.......................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 Recommended Operating Conditions(2) .................... 4
5.3 Thermal Information....................................................4
5.4 Electrical Characteristics.............................................6
5.5 Timing Requirements..................................................6
5.6 Switching Characteristics ...........................................7
5.7 Operating Characteristics........................................... 7
6 Parameter Measurement Information............................ 8
7 Detailed Description........................................................9
7.1 Overview..................................................................... 9
7.2 Functional Block Diagram........................................... 9
7.3 Device Functional Modes............................................9
8 Power Supply Recommendations................................10
9 Layout.............................................................................10
9.1 Layout Guidelines..................................................... 10
10 Device and Documentation Support..........................11
10.1 Receiving Notification of Documentation Updates.. 11
10.2 Support Resources................................................. 11
10.3 Trademarks............................................................. 11
10.4 Electrostatic Discharge Caution.............................. 11
10.5 Glossary.................................................................. 11
11 Mechanical, Packaging, and Orderable
Information.................................................................... 11
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision G (February 2022) to Revision H (June 2022) Page
• Junction-to-ambient thermal resistance values increased. D was 73 is now 117.2, N was 67 is now 89.1........4
Changes from Revision F (September 2003) to Revision G (February 2022) Page
• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards............................................................................................................................. 1
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I TEXAS INSTRUMENTS 3 5 1CLK[1 16]VCC ¥O§§‘U 1K [ 2 15]1CLR ‘— F ‘— 1J [ 3 l4]2CLR 2 I 20 I9 — 1PRE [ 4 |3]2CLK i 4 18E 32:: 1Q [ 5 12]2K 1P5: 5 ”I: NC 1Q[6 ||]2J 1o 6 1:: 2K 20 [ 7 I0]2PRE 15 Q 14[ 2J GND[e 9120 9mu1213 \cgoc NOZN w n: :L N NC 7 N0 Internal oonnecllon
4 Pin Configuration and Functions
J, D, N, W package
16-Pin CDIP, SOIC, PDIP, CFP
Top View
FK Package
20-Pin LCCC
Top View
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 mA
IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ±20 mA
IOContinuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
TJJunction temperature 150 ℃
Tstg Storage temperature range –65 150 ℃
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 Recommended Operating Conditions(2)
SN54HC112 SN74HC112 UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VIH High-level input voltage
VCC = 2 V 1.5 1.5
VVCC = 4.5 V 3.15 3.15
VCC = 6 V 4.2 4.2
VIL Low-level input voltage
VCC = 2 V 0.5 0.5
VVCC = 4.5 V 1.35 1.35
VCC = 6 V 1.8 1.8
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
tt (1) Input transition (rise and fall) time
VCC = 2 V 1000 1000
nsVCC = 4.5 V 500 500
VCC = 6 V 400 400
TAOperating free-air temperature −55 125 −40 85 °C
(1) If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state
from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.
(2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5.3 Thermal Information
THERMAL METRIC
D (SOIC) N (PDIP)
UNIT16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance(1) 117.2 89.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 77.2 46.9 °C/W
RθJB Junction-to-board thermal resistance 75.6 47.4 °C/W
ψJT Junction-to-top characterization parameter 38.1 11.8 °C/W
ψJB Junction-to-board characterization parameter 75.3 47 °C/W
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5.3 Thermal Information (continued)
THERMAL METRIC
D (SOIC) N (PDIP)
UNIT16 PINS 16 PINS
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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5.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC
TA = 25°C SN54HC112 SN74HC112 UNIT
MIN TYP MAX MIN MAX MIN MAX
VOH VI = VIH or VIL
IOH = −20 μA
2 V 1.9 1.998 1.9 1.9
V
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
IOH = −4 mA 4.5 V 3.98 4.3 3.7 3.84
IOH = −5.2 mA 6 V 5.48 5.8 5.2 5.34
VOL VI = VIH or VIL
IOL = 20 μA
2 V 0.002 0.1 0.1 0.1
V
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
IOL = 4 mA 4.5 V 0.17 0.26 0.4 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.4 0.33
IIVI = VCC or 0 6 V ±0.1 ±100 ±1000 ±1000 nA
ICC VI = VCC or 0, IO = 0 6 V 4 80 40 μA
Ci2 V to 6 V 3 10 10 10 pF
5.5 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC
TA = 25°C SN54HC112 SN74HC112 UNIT
MIN MAX MIN MAX MIN MAX
fclock Clock frequency
2 V 5 3.4 4
MHz4.5 V 25 17 20
6 V 29 20 24
twPulse duration
PRE or CLR low
2 V 100 150 125
ns
4.5 V 20 30 25
6 V 17 25 21
CLK high or low
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
tsu Setup time before CLK↓
Data (J, K)
2 V 100 150 125
ns
4.5 V 20 30 25
6 V 17 25 21
PRE or CLR inactive
2 V 100 150 125
4.5 V 20 30 25
6 V 17 25 21
thHold time, data after CLK↓
2 V 0 0 0
ns4.5 V 0 0 0
6 V 0 0 0
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5.6 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Parameter Measurement
Information)
PARAMETER FROM
(INPUT)
TO
(OUTPUT) VCC
TA = 25°C SN54HC112 SN74HC112 UNIT
MIN TYP MAX MIN MAX MIN MAX
fmax
2 V 5 10 3.4 4
MHz4.5 V 25 50 17 20
6 V 29 60 20 24
tpd
PRE or CLR Q or Q
2 V 54 165 245 205
ns
4.5 V 16 33 49 41
6 V 13 28 42 35
CLK Q or Q
2 V 56 125 185 155
4.5 V 16 25 37 31
6 V 13 21 31 26
ttQ or Q
2 V 29 75 110 95
ns4.5 V 9 15 22 19
6 V 8 13 19 16
5.7 Operating Characteristics
TA = 25℃
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load 35 pF
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6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
CL(1)
From Output
Under Test
Test
Point
(1) CL includes probe and test-fixture capacitance.
Figure 6-1. Load Circuit for Push-Pull Outputs
50%
tw
Input 50%
VCC
0 V
Figure 6-2. Voltage Waveforms, Standard CMOS
Inputs Pulse Duration
Clock
Input 50%
VCC
0 V
50% 50%
VCC
0 V
tsu
Data
Input
th
Figure 6-3. Voltage Waveforms, Standard CMOS
Inputs Setup and Hold Times
50%Input 50%
VCC
0 V
50% 50%
VOH
VOL
tPLH(1) tPHL(1)
VOH
VOL
tPHL(1) tPLH(1)
Output
Output 50% 50%
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-4. Voltage Waveforms, Propagation
Delays for Standard CMOS Inputs
VOH
VOL
Output
VCC
0 V
Input
tf(1)
tr(1)
90%
10%
90%
10%
tr(1)
90%
10%
tf(1)
90%
10%
(1) The greater between tr and tf is the same as tt.
Figure 6-5. Voltage Waveforms, Input and Output
Transition Times for Standard CMOS Inputs
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7 Detailed Description
7.1 Overview
The ’HC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to
the outputs on the negative-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is
not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops perform as toggle flip-flops
by tying J and K high.
7.2 Functional Block Diagram
7.3 Device Functional Modes
Table 7-1. Function Table
INPUTS OUTPUTS
PRE CLR CLK J K Q Q
L H X X X H H
H L X X X L H
L L X X X H(1) H(1)
H H ↓ L L Q0Q 0
H H ↓ H L H L
H H ↓ L H L H
H H ↓ H H Toggle
H H H X X Q0Q 0
(1) This configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its
inactive (high) level.
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8 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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10 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 24-Jun-2022
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
84088012A ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84088012A
SNJ54HC
112FK
Samples
8408801EA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8408801EA
SNJ54HC112J Samples
8408801FA ACTIVE CFP W 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8408801FA
SNJ54HC112W Samples
JM38510/65305BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65305BEA Samples
M38510/65305BEA ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 JM38510/
65305BEA Samples
SN54HC112J ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 SN54HC112J Samples
SN74HC112D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC112 Samples
SN74HC112DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC112 Samples
SN74HC112DT ACTIVE SOIC D 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC112 Samples
SN74HC112N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC112N Samples
SNJ54HC112FK ACTIVE LCCC FK 20 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 84088012A
SNJ54HC
112FK
Samples
SNJ54HC112J ACTIVE CDIP J 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8408801EA
SNJ54HC112J Samples
SNJ54HC112W ACTIVE CFP W 16 1 Non-RoHS
& Green SNPB N / A for Pkg Type -55 to 125 8408801FA
SNJ54HC112W Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC112, SN74HC112 :
•Catalog : SN74HC112
•Military : SN54HC112
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
Addendum-Page 2
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LAND PATTERN DATA D (RiPDSOiGiB) PLASTiC SMALL OUTLINE stencil Openings Example Pod Geometry (See Note c) Non Soidermosk Detirled Pad alir 4x1, 27 i 16X0'55ai ‘+l4xi 27 mwannnaia— i6x}v5°--4Er~Eifl{iEr-Hfl-T @E-HnH-a-a— {downgrade r, Example Snider Mask 0 erlin l /l/ i a i 0 07 It (See Note E) All Around ,' 421i233e4/E oa/iz AH linear dimensions are in millimeters This drawing is subject ta anange without notice. Publication che7351 is recommended tar alternate designs. Laser cutting apertures with trapezoidal wail: and also rounding corners will otter better paste release contact tneir board assembly site ror stencil design recommendations, Rerer to ch—7525 tor otner stencil recommendations Customers shouid contact their board lubrication site tor solder musk toierances between and around Signal pods NOTES: Customers should POE”? r" {I} Tums INSTRUMENTS www.li.com
MECHANICAL DATA W (R—GDFP—FWB) CERAM‘C DUAL FLATPACK Base and Seafing Piane 0045 (114) “85 (7-24) I 0.020 (0156) 0.245 (6.22) f I: i i i 0.008 0.20 _ 0.080 2.03) 0.004 (0,i0) 0,055 1.40 47 0,305 (7.75) MAX 4» 0.019 0,48 1 ‘6 i 0.0i5 $0.35; I::I I: T I::I I::I I: :1 3 C I: :1 0430 (i092 : I: 0.370 (9.40) :I I: I: :1 [:3 |::l [:3 |::l “-005 (0-13) MW 4 Piaces [:3 I: i 8 9 T 0350 (9.14) 0.360 (9.14) 0.250 (0.35) 0,250 (6.35) 404018073/F 04/14 NOTES: A. Ail iinsar dimensions are in inches (miiiinisieis). inis drawing is subjeci io cnange wiinoui noiice. This package can be henneiicaiiy seaied Min 0 ceramic Ii'd using glass irit. index point is provided on cap (or lerminai identification oniy. rails wiinin MiL STD i035 00mins r0909? i TEXAS INSTRUMENTS www.mmm
J (R76D1P7TM) CERAVVHC DUAL 1N7L1NE PACKAGE )4 LEADS SHOWN PWS u . W 14 e 18 20 0300 0300 0300 0300 E (7.52) (7.52) (7.62) (7.62) w 5 Est ass ass ass fl fl m m m m m E MAX 0.755 540 0.950 1.060 (19.94) (21.34) (24.35) (25.92) I ..15,,, 1 0 500 0,300 0,310 0.300 U U U U U U U C W (7.52) (7.52) (7.57) (7.52) 0.245 0.245 0.220 0.245 0.005 (1.65) 0 MW 0045 (1.14) (6.22) (6.22) (5.50) (6.22) 0000 ( . ) a «0005(0.13)MN m r ~ 0200 (5.05) MAX 7 ; Seatmg Pmne , 0 (3.30) MN 4 0 020 (0. 66) 0014 (0.36) 0715' 0100 (.)254 0.014 (0.36) 0,000 (0.20) 4040083/F 03/03 VOTES: A. AH Hneur d1mens1ons are 1’1 1mm (muhmeters) a, This druwmg '3 subject m change w'thout nnt'ce. 0, 1m package 15 hermehcoHy sewed mm a cemm 11a usmg q1ass mt. D. 11an pom 1’s prowded on cap fo' 1mm) 1den1111ca0an umy on press cemrmc 9055 m sea) 00W. E FaHs thin ML 513 1035 0011417114. 001141416. GDPPTTB 0'10 001017120
MECHANICAL DATA N (R—PDlP-T“) PLASTIC DUAL—IN—LINE PACKAGE 16 P15 SHOWN PWS " A L . [NM 15 a 20 16 9 0 775 U 777 0 SZU '1 USE 3 , 1H HH HH r% r’H r"—1 r’H H1 1 A VAX “9‘69? (191591 (23,37) (25,92) 0 250 (6,50‘ A MN [1145‘ 0142‘ 0.350 new 3 O 240 (6.10), 15 92/ (1832/ (2 .59) (23,58) MSiUO‘ (A AA AA Ari AA AA AA R1 &. VAR1AT1CN M RR AC AD 1 B 0070( (17s) 0015 (111) A 0045 (1,111 g n > , ‘ -) 3.020 (0,51) MW w o 5 (0 35) 0200( 38) MAX f, ), Gnu E Home 1 1‘ 9 fix—1%)” 1 0125’ 1/111 4% 0010 (v.37 ) NOM 31a) U L»- J 0450 (13,92) MAX L 202‘ (0,53) » e c 015 (0,35) / \ a; 00‘s (0,Zb)® / \ 1 1 \\¥,// 11/18 Pm (My > @ 20 Pm vendor upho'v mom/r 17/7037 NO'FS A AH Mnec' mmensmr‘fi: B 1m: drawmq 1s sume m muss (m1111mevem) 0 change mm): nofice /c\ FuHs wumn JEDEC M57001, except 15 an: 20 p171 'r1111mLm body 1mm (01m A) A The 70 p171 and 15m} shmflder Md” 15 a ve'vdnr 0311071, eher NIH Dr 111 wkflh INSI'RUMENTS www.1i.com
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