TLV2369, TLV2369 Datasheet by Texas Instruments

I TEXAS INSTRUMENTS um CommonrMode Vouage (V)
Normalized μOffset Voltage ( V)
100
80
60
40
20
0
–20
–40
–60
–80
–100
Common-Mode Voltage (V)
–0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
10 Typical Units Shown
V = 5 V
S
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV369
,
TLV2369
SBOS757 –MAY 2016
TLVx369 Cost-Optimized, 800-nA, 1.8-V, Rail-to-Rail I/O
Operational Amplifier with Zero-Crossover Distortion
1
1 Features
1• Cost-Optimized Precision Amplifier nanoPower:
800 nA/Ch (Typ)
• Low Offset Voltage: 400 µV (Typ)
• Rail-to-Rail Input and Output
• Zero-Crossover Distortion
• Low Offset Drift: 0.5 µV/°C (Typ)
• Gain-Bandwidth Product: 12 kHz
• Supply Voltage: 1.8 V to 5.5 V
•microSize Packages: SC70-5, VSSOP-8
2 Applications
• Blood Glucose Meters
• Test Equipment
• Low-Power Sensor Signal Conditioning
• Portable Devices
3 Description
The TLV369 family of single and dual operational
amplifiers represents a cost-optimized generation of
1.8-V nanopower amplifiers.
With the zero-crossover distortion circuitry, these
amplifiers feature high linearity over the full common-
mode input range with no crossover distortion,
enabling true rail-to-rail input and operating from a
1.8-V to 5.5-V single supply. The family is also
compatible with industry-standard nominal voltages of
3.0 V, 3.3 V, and 5.0 V.
The TLV369 (single version) is offered in a 5-pin
SC70 package. The TLV2369 (dual version) comes in
8-pin VSSOP and SOIC packages.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TLV369 SC70 (5) 2.00 mm × 1.25 mm
TLV2369 VSSOP (8) 3.00 mm × 3.00 mm
SOIC (8) 4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
TLV369 Family Eliminates Crossover Distortion
Across the Full Supply Range
l TEXAS INSTRUMENTS
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information: TLV369 ................................... 5
6.5 Thermal Information: TLV2369 ................................. 5
6.6 Electrical Characteristics........................................... 6
6.7 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 11
8 Application and Implementation ........................ 12
8.1 Application Information............................................ 12
8.2 Typical Application .................................................. 12
8.3 System Examples .................................................. 14
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1 Documentation Support ....................................... 17
11.2 Community Resources.......................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
DATE REVISION NOTES
May 2016 * Initial release.
*9 TEXAS INSTRUMENTS j j C C C
1
2
3
4
8
7
6
5
V+
OUTB
-INB
+INB
OUTA
-INA
+INA
V-
1
2
3
4
8
7
6
5
OUT A
-IN A
+IN A
V-+IN B
-IN B
OUT B
V+
1
2
3
5
4
V+
OUT
+IN
V-
-IN
3
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5 Pin Configuration and Functions
TLV369: DCK Package
5-Pin SC70
Top View
Pin Functions: TLV369
PIN
I/O DESCRIPTION
NAME TLV369
DCK (SC70)
–IN 3 I Negative (inverting) input
+IN 1 I Positive (noninverting) input
OUT 4 O Output
V– 2 — Negative (lowest) power supply or ground (for single-supply operation)
V+ 5 — Positive (highest) power supply
TLV2369: D Package
8-Pin SOIC
Top View
TLV2369: DGK Package
8-Pin VSSOP
Top View
Pin Functions: TLV2369
PIN
I/O DESCRIPTION
NAME
TLV2369
D (SOIC) DGK
(VSSOP)
–IN A 2 2 I Inverting input, channel A
–IN B 6 6 I Inverting input, channel B
+IN A 3 3 I Noninverting input, channel A
+IN B 5 5 I Noninverting input, channel B
OUT A 1 1 O Output, channel A
OUT B 7 7 O Output, channel B
V– 4 4 — Negative (lowest) power supply
V+ 8 8 — Positive (highest) power supply
l TEXAS INSTRUMENTS
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
(3) Short-circuit to VS/ 2, one amplifier per package.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Supply, VS= (V+) – (V–) 0 +7 V
Signal input pin(2) (V–) – 0.5 (V+) + 0.5 V
Current Signal input pin(2) –10 10 mA
Output short-circuit(3) Continuous mA
Temperature
Operating, TA–40 125 °C
Junction, TJ150 °C
Storage, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted).
VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted).
MIN NOM MAX UNIT
VSSupply voltage 1.8 5.5 V
Specified temperature –40 85 °C
l TEXAS INSTRUMENTS
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information: TLV369
THERMAL METRIC(1)
TLV369
UNITDCK (SC70)
5 PINS
RθJA Junction-to-ambient thermal resistance 293.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 95.2 °C/W
RθJB Junction-to-board thermal resistance 83.4 °C/W
ψJT Junction-to-top characterization parameter 2.9 °C/W
ψJB Junction-to-board characterization parameter 82.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Thermal Information: TLV2369
THERMAL METRIC(1)
TLV2369
UNITD (SOIC) DGK (VSSOP)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 121.5 168.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 66.3 58.1 °C/W
RθJB Junction-to-board thermal resistance 62.5 88.9 °C/W
ψJT Junction-to-top characterization parameter 22.8 9.3 °C/W
ψJB Junction-to-board characterization parameter 61.9 87.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
l TEXAS INSTRUMENTS
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6.6 Electrical Characteristics
VS(total supply voltage) = 1.8 V to 5.5 V; at TA= 25°C, and RL= 100 kΩconnected to VS/ 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage At TA= 25°C 0.4 2 mV
At TA= –40°C to +85°C 0.85
dVOS/dT Drift At TA= –40°C to +85°C 0.5 μV/°C
PSRR Power-supply rejection ratio VS= 1.8 V to 5.5 V 80 94 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage range V– V+ V
CMRR Common-mode rejection ratio (V–) ≤VCM ≤(V+) 80 110 dB
INPUT BIAS CURRENT
IBInput bias current At TA= 25°C 10 pA
At TA= –40°C to +85°C See Figure 8
IOS Input offset current 10 pA
INPUT IMPEDANCE
ZID Differential 1013 || 3 Ω|| pF
ZIC Common-mode 1013 || 6 Ω|| pF
NOISE
EnInput voltage noise f = 0.1 Hz to 10 Hz 4 μVPP
enInput voltage noise density f = 1 kHz 300 nV/√Hz
inInput current noise density f = 1 kHz 1 fA/√Hz
OPEN-LOOP GAIN
AOL Open-loop voltage gain
At VS= 5.5 V, 100 mV ≤VO≤(V+) – 100 mV,
RL= 100 kΩ130
dB
At VS= 5.5 V, 500 mV ≤VO≤(V+) – 500 mV,
RL= 10 kΩ80 120
OUTPUT
VOVoltage output swing from rail RL= 10 kΩ25 mV
ISC Short-circuit current 10 mA
CLOAD Capacitive load drive See Figure 10
FREQUENCY RESPONSE
GBP Gain bandwidth product 12 kHz
SR Slew rate G = 1 0.005 V/µs
tOR Overload recovery time VIN × gain = VS250 µs
POWER SUPPLY
VSSpecified voltage range 1.8 5.5 V
IQQuiescent current IO= 0 mA, at VS= 5.5 V 800 1300 nA
TEMPERATURE
Specified range –40 85 °C
TAOperating range –40 125 °C
l TEXAS INSTRUMENTS mu CommanrMude Vul‘age (V) mm (500 msldw) 140 180 3 Frequency (Hz) Temperamre ('c) 120 Frequency (Hz) Temperamre (“0)
120
100
80
60
40
20
0
Frequency (Hz)
CMRR (dB)
10 10k1k100 20k
140
120
100
80
60
40
20
0
–20
Frequency (Hz)
Gain (dB)
0.001 100 1k100.1 10.01 20k10k
Phase
Gain
180
135
90
45
0
Phase (°)
3
2.5
2
1.5
1
0.5
0
Temperature (°C)
A ( V/V)μ
OL
–75 –50 –25 0 25 50 75 100 125
R = 10 kΩ
L
R = 100 kΩ
L
Normalized μOffset Voltage ( V)
100
80
60
40
20
0
–20
–40
–60
–80
–100
Common-Mode Voltage (V)
–0.2
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
3.8
4
4.2
4.4
4.6
4.8
5
5.2
1 V/divm
Time (500 ms/div)
7
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6.7 Typical Characteristics
at TA= 25°C, VS= 5 V, and RL= 100 kΩconnected to VS/ 2 (unless otherwise noted)
10 typical units shown, VS= 5 V
Figure 1. Normalized Offset Voltage vs
Common-Mode Voltage
Figure 2. 0.1-Hz to 10-Hz Noise
VS= 5.5 V
Figure 3. Open-Loop Gain and Phase vs Frequency Figure 4. Open-Loop Gain vs Temperature
Figure 5. Common-Mode Rejection Ratio vs Frequency Figure 6. Output Voltage Swing from Rail vs Temperature
l TEXAS INSTRUMENTS Frequency Hz) 10k Temperature ('c) 106 Frequency (Hz) Capacmve Load (pF) Tune (mu us/dw) Tune (250 us/mw
20 mV/div
Time (100 s/div)μ
500 mV/div
Time (250 s/div)μ
10G
1G
100k
10k
1k
100
10
Frequency (Hz)
0 1G10
Z ( )Ω
O
100 1k 10k 100k
20
18
16
14
12
10
8
6
4
2
0
Capacitive Load (pF)
Overshoot (%)
10 100
G = 1
G = –1
Input Bias Current (pA)
–50
10k
1k
100
10
1
0.1
0.01
Temperature (°C)
125–25 0 25 50 75 100
3
2.5
2
1.5
1
0.5
0
Frequency (Hz)
Maximum V (V)
OUT
100 1k 2k
8
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Typical Characteristics (continued)
at TA= 25°C, VS= 5 V, and RL= 100 kΩconnected to VS/ 2 (unless otherwise noted)
Figure 7. Maximum Output Voltage vs Frequency Figure 8. Input Bias Current vs Temperature
Figure 9. Open-Loop Output Impedance vs Frequency Figure 10. Small-Signal Overshoot vs Capacitive Load
CL= 20 pF
Figure 11. Small-Signal Step Response Figure 12. Large-Signal Step Response
l TEXAS INSTRUMENTS Tune (sun us/dw)
1 V/div
Time (500 s/div)μ
Input
Output
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Typical Characteristics (continued)
at TA= 25°C, VS= 5 V, and RL= 100 kΩconnected to VS/ 2 (unless otherwise noted)
Figure 13. Overload Recovery
l TEXAS INSTRUMENTS TV LA <0>
Bias Circuitry
Input Stage Load
Low-Noise
Charge Pump
Bias Circuitry
+IN
-IN
OUT
V+
V-
10
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7 Detailed Description
7.1 Overview
The TLVx369 family of operational amplifiers minimizes power consumption and operates on supply voltages as
low as 1.8 V. The zero-crossover distortion circuitry enables high linearity over the full input common-mode
range, achieving true rail-to-rail input from a 1.8-V to 5.5-V single supply.
7.2 Functional Block Diagram
l TEXAS INSTRUMENTS AcurrenHlmmng reswslur .s reqwea .1 «he mput vanage Cupyngm© 2am Texas \nskumems \ncnrpora‘ed
5 kW
10 mA, max
5 V
VIN
VOUT
IOVERLOAD
A current-limiting resistor is required if the input voltage
exceeds the supply rails by 0.5 V.³
TLV369
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7.3 Feature Description
7.3.1 Operating Voltage
The TLV369 series os op amps are fully specified and tested from 1.8 V to 5.5 V (±0.9 V to ±2.75 V). Parameters
that vary significantly with supply voltage are described in the Typical Characteristics section.
7.3.2 Input Common-Mode Voltage Range
The TLV369 family is designed to eliminate the input offset transition region typically present in most rail-to-rail,
complementary-stage operational amplifiers, allowing the TLV369 family of amplifiers to provide superior
common-mode performance over the entire input range.
The input common-mode voltage range of the TLV369 family typically extends to each supply rail. CMRR is
specified from the negative rail to the positive rail; see Figure 1,Normalized Offset Voltage vs Common-Mode
Voltage.
7.3.3 Protecting Inputs from Overvoltage
Input currents are typically 10 pA. However, large inputs (greater than 500 mV beyond the supply rails) can
cause excessive current to flow in or out of the input pins. Therefore, in addition to keeping the input voltage
between the supply rails, the input current must also be limited to less than 10 mA. This limiting is easily
accomplished with an input resistor, as shown in Figure 14.
Figure 14. Input Current Protection for Voltages That Exceed the Supply Voltage
7.4 Device Functional Modes
The TLV369 family has a single functional mode. These devices are powered on as long as the power-supply
voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).
l TEXAS INSTRUMENTS
VSUP+
+VOUT
RF
VIN
RI
VSUP-
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
When designing for ultra-low power, choose system components carefully. To minimize current consumption,
select large-value resistors. Any resistors can react with stray capacitance in the circuit and the input capacitance
of the operational amplifier. These parasitic RC combinations can affect the stability of the overall system. Use of
a feedback capacitor assures stability and limits overshoot or gain peaking.
8.2 Typical Application
A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 15. An inverting
amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative
voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on
the output. In addition, amplification can be added by selecting the input resistor RIand the feedback resistor RF.
Figure 15. Application Schematic
8.2.1 Design Requirements
The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The
limits of the input common-mode range (VCM) and the output voltage swing to the rails (VO) must also be
considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at
±2.5 V is sufficient to accommodate this application.
l TEXAS INSTRUMENTS A \N A 1 .8 6 70 .5 Twme
Time
Voltage (V)
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2Input
Output
F
VI
R
AR
V1.8
A 3.6
0.5
OUT
VIN
V
AV
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Typical Application (continued)
8.2.2 Detailed Design Procedure
Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:
(1)
(2)
When the desired gain is determined, choose a value for RIor RF. Choosing a value in the kilohm range is
desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This
milliamp current range ensures that the device does not draw too much current. The trade-off is that very large
resistors (100s of kilohms) draw the smallest current but generate the highest noise. Very small resistors (100s of
ohms) generate low noise but draw high current. This example uses 10 kΩfor RI, meaning 36 kΩis used for RF.
These values are determined by Equation 3:
(3)
8.2.3 Application Curve
Figure 16. Inverting Amplifier Input and Output
l TEXAS INSTRUMENTS 7% H 1.2V 2 24 M52 2 20 MG H H a
R =
BIAS = 0.9 MW
VBATTMIN
IBIAS
=1.8 V
2 Am
R =
2
-
VTHRS
VBATT
1
R1
1
( )
-1
R1
=
-
2 V
1.2 V 420 kW
´
1
420 kW
1
( )
-1
20 MW
= 650 kW
R = R
1F= 20 MW
VHYST
VBATT
= 420 kW
50 mV
2.4 V
R =
F
VREF
1000 (IBMAX)
=1.2 V
1000 (50 pA)
= 24 M 20 MW W»
REF1112
TLV369
+IN
OUT
-IN VSTATUS
VBATT
VREF
R1
R2
RBIAS
IBIAS
RF
+
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8.3 System Examples
8.3.1 Battery Monitoring
The low operating voltage and quiescent current of the TLV369 series make the family an excellent choice for
battery-monitoring applications, as shown in Figure 17.
Figure 17. Battery Monitor
In this circuit, VSTATUS is high as long as the battery voltage remains above 2 V. A low-power reference is used to
set the trip point. Resistor values are selected as follows:
1. Selecting RF: Select RFsuch that the current through RFis approximately 1000 times larger than the
maximum bias current over temperature, as given by Equation 4:
(4)
2. Choose the hysteresis voltage, VHYST. For battery-monitoring applications, 50 mV is adequate.
3. Calculate R1as calculated by Equation 5:
(5)
4. Select a threshold voltage for VIN rising (VTHRS) = 2.0 V.
5. Calculate R2as given by Equation 6:
(6)
6. Calculate RBIAS: The minimum supply voltage for this circuit is 1.8 V. The REF1112 has a current
requirement of 1.2 μA (max). Providing the REF1112 with 2 μA of supply current assures proper operation.
Therefore, RBIAS is as given by Equation 7.
(7)
l TEXAS INSTRUMENTS V R v 2 R‘ + R2
V =
L
R4
R + R
3 4
V =
H
R2
R + R
1 2
3 V
A1
A2
D1(2)
D2(2)
R5
10 kW
R6
5.1 kW
R7
5.1 kW
RIN
2 kW(1)
3 V
3V
Q1(3)
R1
VH
VL
R2
1/2
TLV2369
1/2
TLV2369
3 V
VOUT
VIN
3 V
R3
R4
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System Examples (continued)
8.3.2 Window Comparator
Figure 18 shows the TLV2369 used as a window comparator. The threshold limits are set by VHand VL, with VH
greater than VL. When VIN is less than VH, the output of A1 is low. When VIN is greater than VL, the output of A2
is low. Therefore, both op amp outputs are at 0 V as long as VIN is between VHand VL. This architecture results
in no current flowing through either diode, Q1 is in cutoff, with the base voltage at 0 V, and VOUT forced high.
Figure 18. TLV2369 as a Window Comparator
If VIN falls below VL, the output of A2 is high, current flows through D2, and VOUT is low. Likewise, if VIN rises
above VH, the output of A1 is high, current flows through D1, and VOUT is low. The window comparator threshold
voltages are set as shown by Equation 8 and Equation 9:
(8)
(9)
9 Power Supply Recommendations
The TLV369 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant
variance with regard to operating voltage or temperature.
CAUTION
Supply voltages larger than 7 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement; see the Layout
Guidelines section.
l TEXAS INSTRUMENTS
+
VIN VOUT
RG
RF
Copyright © 2016, Texas Instruments Incorporated
±IN
+IN
V±
VS+
GND
VS±
GND
VOUT
VIN
Run the input traces as
far away from the supply
lines as possible.
Use a low-ESR, ceramic
bypass capacitor.
RF
RG
Place components close to the device and
to each other to reduce parasitic errors.
Use a low-ESR,
ceramic bypass
capacitor. OUT
V+
Copyright © 2016, Texas Instruments Incorporated
16
TLV369
,
TLV2369
SBOS757 –MAY 2016
www.ti.com
Product Folder Links: TLV369 TLV2369
Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of the circuitry is one of the simplest and most
effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to
ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI)
noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of
the ground current. For more detailed information, see Circuit Board Layout Techniques,SLOA089.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than crossing in parallel with the noisy trace.
• Place the external components as close to the device as possible. Keep RFand RGclose to the inverting
input in order to minimize parasitic capacitance, as shown in Figure 19.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 19. Operational Amplifier Board Layout for Noninverting Configuration
Figure 20. Schematic Representation of Figure 19
l TEXAS INSTRUMENTS
17
TLV369
,
TLV2369
www.ti.com
SBOS757 –MAY 2016
Product Folder Links: TLV369 TLV2369
Submit Documentation FeedbackCopyright © 2016, Texas Instruments Incorporated
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
The following documents are relevant to using the TLVx369, and are recommended for reference and available
for download at www.ti.com, unless otherwise noted.
• REF1112 Data Sheet, SBOS283
•Circuit Board Layout Techniques,SLOA089
•Handbook of Operational Amplifier Applications,SBOA092
•Analog Engineer's Pocket Reference,SLWY038
11.1.1.1 Related Links
Table 1 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL
DOCUMENTS TOOLS &
SOFTWARE SUPPORT &
COMMUNITY
TLV369 Click here Click here Click here Click here Click here
TLV2369 Click here Click here Click here Click here Click here
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
I TEXAS INSTRUMENTS Samples Samples Samples Samples Samples
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
TLV2369IDGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 13JV
TLV2369IDGKT ACTIVE VSSOP DGK 8 250 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 13JV
TLV2369IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TL2369
TLV369IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12K
TLV369IDCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 12K
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«Pt» Reel Diameter AD Dimension designed to accommodate the component Width ED Dimension destgned to accommodate the component tengtti K0 Dimension designed to accommodate the component thickness 7 W OveraH wtdlh loe earner tape i P1 Pttch between successwe cavtty centers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE OOODOODD ,,,,,,,,,,, ‘ User Direcllon 0' Feed Sprocket Hoies Pockel Quadrants
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV2369IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2369IDGKT VSSOP DGK 8 250 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV2369IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV369IDCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
TLV369IDCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Nov-2020
Pack Materials-Page 1
I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV2369IDGKR VSSOP DGK 8 2500 366.0 364.0 50.0
TLV2369IDGKT VSSOP DGK 8 250 366.0 364.0 50.0
TLV2369IDR SOIC D 8 2500 853.0 449.0 35.0
TLV369IDCKR SC70 DCK 5 3000 180.0 180.0 18.0
TLV369IDCKT SC70 DCK 5 250 180.0 180.0 18.0
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Nov-2020
Pack Materials-Page 2
MECHANICAL DATA DCK (R—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE E was 5 47 Fl Fl f f 240 \ ,i, w 1,80 1,10 Pm/ \ ‘ $ ‘ . maexArea Wm H 1* MO Um Gauge Mane Seanng Mane fit Scam Mane gig/Em 409555575/8 U‘ /200/ , m m hmeters NO'FS AH \mec' dwmensiur: Umm> FuHs an JFDFC M07763 vunuhcn AA Tm drawmq \s sumsc: 0 change wmu: nome Body mmensmns do nut mc‘ude mom flcsh m aroms'm Mom Has» and pruvuswon W m exceed 015 :2r m INSrRUMEm-s www.1i.com
LAND PATTERN DATA DC< (="" 7pjsoic5=""> PLASTC SMALL OU’LME Exc'm‘e Boc'd LuyuM stem Openings Based or a stencfl tn'ckndss uf 127mm (005m) /23\\der Musk Cpen'v‘g d d s W \‘ ‘\“=bd Geometry \ v y \ NOTES- A M \meur dimensmns are m miHWete's a. In: druwv‘q is sweat (a chc'vge mud: 'vuhce c Custume's snodd p‘uce d note 01 me mm: buurd (abr'cahun c'awmg nm :0 mm the ce'fle' smder musk denned Dad, n mundmn many is reco'n'nended (Dr uHernme designs EV Laser cumrq opc'mvcs wnn "apczmda wuHs and mo rouncmq corners wm am bcncr dosxc readscv Cdstomcrs shou‘c can thew Guard asse’na‘y me for Ska design recom’nencnhons EXONP‘S s‘ercfl des‘g’v baSeC on a 50% vo‘umemc \Dud su‘der paste M‘cr m H’C’ bk) Var other S‘cncfl rccowmcwdatnrs. ' hams Q‘ INSTRUMENTS www.li.com
‘J
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
Yl“‘+
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA DGK (S—PDSO—GS) PLASTIC SMALL—OUTLINE PACKAGE m1 WW“: {[0 VAX % j 3,010 I 4073329/E 05/06 NO'ES' A AH imec' dimensmrs c'e m m'hmeiers 5 Th: drawing is enmec: :e change within: nciice. Body icnqth Coos mi mciucc maid Hash, protrusions or we tms Mom 'iush, aromons, ov qaw burrs shaH m exceed 015 per end b Budy mm does not wcude inierieud flasi‘ inieriead ‘iush s'mii 'mi exceed 050 pe' we : FuHs wiUHn JEDEC M0487 quulion AA, except 'vievieud ricer INSTRUMENTS w. (i. com
LAND PATTERN DATA DGK (37PD30708) PLASTIC SMALL OUTLINE PACKAGE Exampie Board Layout Exampie stencii Openings Based on a stencii thickness of .127mm L005inch), (See Nate 0) (,0 65) TYP ‘ Li 5 LLLLL L, pm ,,,,, PKG PKG "\ i i 4 — ----- i — ----- i D DU D i i ’ PKG PKG Q G . / Exampie , Non Soldermusk Defined Pad i , , —\ L A ~/ ‘\ Example \ Spider Musk Opening / +1 1‘(0,45) ‘ (See Note E) t 1 (1,45) < ‘="" \pud="" geometry="" ’="" (see="" note="" c)="" \="" +ii¢="" (0,05)="" \="" ah="" around="" «="" ,="" \="" e="" ’="" i="" ‘\-=""> muss/A 11/13 NOTES: A. Ali iinear dimensions are in miilimeters. a. This drawing is subject ta change without natiee, C, Publication |PCi7351 is recommended ior alternate designsu a. Laser cutting apertures with trapezoidui walls and aisa rounding corners w‘iH ofler eetter paste veiease. Customers snouid Contact their board ussembiy site for stencii design recommendations. Rater tn IFS—7525 for other slenci'i recummendutions. Customers should Contact their tmurd fabrication site for solder musk tolerances between and around signal pads. .r'I {I TEXAS INSTRUMENTS www.li.com
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